even_odd.vhd

VHDL实现的奇偶校验功能模块和一个外设配置寄存器的设计实例。

library ieee;
use ieee.std_logic_1164.all;

entity even_odd is
	port(
		datain:in std_logic_vector(31 downto 0);
		par:out std_logic;
		clk:in std_logic
		);
end even_odd;

architecture behave of even_odd is
	--signal even:std_logic;
	begin

		process(datain)
		variable even:std_logic;
			begin
				even:='0';
				for i in datain'range loop
					if datain(i)='1' then
						even:=not even;
					end if;
				end loop;
				
				
				if rising_edge(clk) then
					par<=even;
				end if;
		end process;
end behave;