代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/296104/8121599
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/296097/8122102
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/244507/12859062
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/244458/12863481
v p0test.v
module P0test(datain,dataout);
input[7:0] datain;
output[7:0] dataout;
reg[7:0] dataout;
always@(datain)
begin
dataout=datain;
end
endmodule
www.eeworm.com/read/143521/12868103
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/142672/12931069
vhd test_stream.vhd
library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture arch_test of test is
component code_stream is
generic(for_detec:std_logic_vector:="11100");
port(clk:in st
www.eeworm.com/read/326116/13165094
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/324473/13261430
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/137539/13313754
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/318986/13464684
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i