代码搜索：counters
找到约 1,049 项符合「counters」的源代码
代码结果 1,049
www.eeworm.com/read/243541/12934983
v counters_altera.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, ena
www.eeworm.com/read/489686/6468787
v counters_altera.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, ena
www.eeworm.com/read/263314/11367849
vhd counters_altera.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/401301/11559707
v counters_altera.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, ena
www.eeworm.com/read/341658/12074371
vhd counters_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package counters_pkg is
component ascount
generic(countersize:integer:=2);
port(clk,areset,sreset,enable:in std_logic;
www.eeworm.com/read/254980/12110157
v counters_altera.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, ena