代码搜索：combinatorial
找到约 224 项符合「combinatorial」的源代码
代码结果 224
www.eeworm.com/read/399935/7821068
v proc.v
// MAX+plus II Verilog Example
// Combinatorial Always Statement
// Copyright (c) 1994 Altera Corporation
module proc (d, q);
input [2:0] d;
output [1:0] q;
integer num_bits;
www.eeworm.com/read/399935/7821178
vhd proc.vhd
-- MAX+plus II VHDL Example
-- Combinatorial Process Statement
-- Copyright (c) 1994 Altera Corporation
ENTITY proc IS
PORT
(
d : IN BIT_VECTOR (2 DOWNTO 0);
q : OUT INTEGER RANGE 0 TO
www.eeworm.com/read/300949/13879030
frp dk3200_1.frp
******************************************************************************************
PSDsoft Express Version 8.10
Output of PS
www.eeworm.com/read/300949/13879318
frp dk3200_1.frp
******************************************************************************************
PSDsoft Express Version 8.10
Output of PS
www.eeworm.com/read/124394/6050141
v generic_fifo_sc_a.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock
www.eeworm.com/read/345013/11846578
frp shuikong.frp
******************************************************************************************
PSDsoft Express Version 8.50
Output of PS
www.eeworm.com/read/126327/14428474
v proc.v
// MAX+plus II Verilog Example
// Combinatorial Always Statement
// Copyright (c) 1994 Altera Corporation
module proc (d, q);
input [2:0] d;
output [1:0] q;
integer num_bits;
www.eeworm.com/read/126327/14428580
vhd proc.vhd
-- MAX+plus II VHDL Example
-- Combinatorial Process Statement
-- Copyright (c) 1994 Altera Corporation
ENTITY proc IS
PORT
(
d : IN BIT_VECTOR (2 DOWNTO 0);
q : OUT INTEGER RANGE 0 TO
www.eeworm.com/read/476030/6772705
vhd proc.vhd
-- MAX+plus II VHDL Example
-- Combinatorial Process Statement
-- Copyright (c) 1994 Altera Corporation
ENTITY proc IS
PORT
(
d : IN BIT_VECTOR (2 DOWNTO 0);
q : OUT INTEGER RANGE 0 TO
www.eeworm.com/read/476033/6772724
v proc.v
// MAX+plus II Verilog Example
// Combinatorial Always Statement
// Copyright (c) 1994 Altera Corporation
module proc (d, q);
input [2:0] d;
output [1:0] q;
integer num_bits;