📄 shuikong.frp
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PSDsoft Express Version 8.50
Output of PSD Fitter
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PROJECT : shuikong DATE : 03/17/2006
DEVICE : uPSD3254BV TIME : 09:35:42
FIT OPTION : Keep Current
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==== Pin Layout for U (80-Pin TQFP) Package Type ====
-----------------------------
| |
WIND |1 ] pd2 adio4 [41| Address Bus a4/Data Port d4, ad4
|2 ] p3_3 p3_5 [42|
USB_CS |3 ] pd1 adio5 [43| Address Bus a5/Data Port d5, ad5
ale |4 ] pd0 p3_6 [44|
SMC8 |5 ] pc7 adio6 [45| Address Bus a6/Data Port d6, ad6
tdo, TDO |6 ] pc6/TDO p3_7 [46|
tdi, TDI |7 ] pc5/TDI adio7 [47| Address Bus a7/Data Port d7, ad7
|8 ] N/C Xtal1 [48| Xtal1
CEFS |9 ] pc4/TERR Xtal2 [49| Xtal2
|10] N/C VCC [50|
|11] N/C adio8 [51| Address Bus a8, a8
|12] VCC p1_0 [52|
|13] GND adio9 [53| Address Bus a9, a9
SRAMCS |14] pc3/TSTAT p1_1 [54|
CSPLD |15] pc2 adio10 [55| Address Bus a10, a10
tck, TCK |16] pc1/TCK p1_2 [56| UART2_RxD
|17] N/C adio11 [57| Address Bus a11, a11
A19 |18] p4_7 p1_3 [58| UART2_TxD
A18 |19] p4_6 p1_4 [59| TH_SIG
tms, TMS |20] pc0/TMS p1_5 [60| MARK
SMDET |21] pa7 p1_6 [61| PAPER
PT_le |22] pa6 cntl0 [62| _wr
A17 |23] p4_5 cntl2 [63| _psen
AD14 |24] pa5 p1_7 [64| BUSY
A16 |25] p4_4 cntl1 [65| _rd
AD13 |26] pa4 pb7 [66| rd_cpld
A15 |27] p4_3 pb6 [67| USB_INT
AD12 |28] pa3 Reset_In [68| _Reset_In
|29] GND GND [69|
SM_DET |30] p4_2 Vref [70| VREF
SMIOCLK |31] p4_1 N/C [71|
smclk |32] pa2 pb5 [72| CS1
SMC4 |33] p4_0 pb4 [73| K_DI
simclk |34] pa1 pb3 [74| VFD_STB
clkcard |35] pa0 p3_0 [75| UART1_RxD
ad0, Address Bus a0/Data Port d0 |36] adio0 pb2 [76| VFD_SCK
ad1, Address Bus a1/Data Port d1 |37] adio1 p3_1 [77| UART1_TxD
ad2, Address Bus a2/Data Port d2 |38] adio2 pb1 [78| VFD_DO
ad3, Address Bus a3/Data Port d3 |39] adio3 p3_2 [79|
HOME_P |40] p3_4 pb0 [80| EN_LCD
| |
-----------------------------
==== Global Configuration ====
Data Bus : 8-Bit
Address/Data Mode : Multiplexed
ALE/AS Signal : Active High
Control Signals : /WR, /RD, /PSEN
Main PSD flash memory will reside in this space at power-up : Data space
Secondary PSD flash memory will reside in this space at power-up : Program space
Enable Chip-Select Input(/CSI) : OFF
Standby Voltage Input (PC2) : OFF
Standby-on Indicator (PC4) : OFF
RDY/Busy function (PC3) : OFF
Load Micro-Cell on : edge
Security Protection : OFF
==== DataBus_IMC access information ====
CSIOP
Location Address Offset Register Name Signals
--------------------------------------------------------
===== Resource Usage Summary =====
Total Product Terms Used: 68
Device Resources used / total
------------------------------------------------
Port A: (pins 35 34 32 28 26 24 22 21)
I/O Pins : 8 / 8
GP I/O or Address Out : 1
Peripheral I/O : 0
Logic Inputs : 1
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 6
Registered Outputs : 0
Other Information
Microcells : 8 / 8
Micro-Cells AB :
Buried Microcells : 2
Output Microcells : 6
Product Terms : 8 / 24
Control Product Terms : 12 / 34
Port B: (pins 80 78 76 74 73 72 67 66)
I/O Pins : 8 / 8
GP I/O or Address Out : 6
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 2
Registered Outputs : 0
Other Information
Microcells : 8 / 8
Micro-Cells AB :
Buried Microcells : 6
Output Microcells : 0
Micro-Cells BC :
Buried Microcells : 0
Output Microcells : 2
Product Terms : 8 / 26
Control Product Terms : 9 / 34
Port C: (pins 20 16 15 14 9 7 6 5)
I/O Pins : 8 / 8
GP I/O or Address Out : 1
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
JTAG signals : 4
Standby Voltage Input : 0
Rdy/Bsy signal : 0
Standby On Indicator : 0
Combinatorial Outputs : 3
Registered Outputs : 0
Other Information
Microcells : 7 / 8
Micro-Cells BC :
Buried Microcells : 4
Output Microcells : 3
Product Terms : 11 / 32
Control Product Terms : 6 / 34
Port D: (pins 4 3 1)
I/O Pins : 3 / 3
GP I/O or Address Out : 1
Logic Inputs : 0
Chip-Select Input : 0
Clock Input : 0
Control Signal Input : 1
Fast Decoding Outputs : 1
Other Information
Product Terms : 1 / 3
Control Product Terms : 1 / 3
==== OMC Resource Assignment ====
Resources PT User
Used Allocation Name
---------------------------------------------------------
Micro-Cell AB :
Micro-Cells 0 - CNT1 => Register
Micro-Cells 1 - simclk (mcellab1) => Combinatorial
Micro-Cells 2 - smclk (mcellab2) => Combinatorial
Micro-Cells 3 - AD12 (mcellab3) => Combinatorial
Micro-Cells 4 - AD13 (mcellab4) => Combinatorial
Micro-Cells 5 - AD14 (mcellab5) => Combinatorial
Micro-Cells 6 - PT_le (mcellab6) => Combinatorial
Micro-Cells 7 - CNT0 => Register
Micro-Cell BC :
Micro-Cells 0 - CNT2 => Register
Micro-Cells 1 - rs0_0 => Combinatorial
Micro-Cells 2 - CSPLD (mcellbc2) => Combinatorial
Micro-Cells 3 - SRAMCS (mcellbc3) => Combinatorial
Micro-Cells 4 - CEFS (mcellbc4) => Combinatorial
Micro-Cells 5 - CS1 (mcellbc5) => Combinatorial
Micro-Cells 7 - rd_cpld (mcellbc7) => Combinatorial
External Chip Select :
Fast Chip Select 1 - USB_CS (ecsd1) => Fast Decoding
========= Equations =========
DPLD EQUATIONS :
=======================
fs0 = (!pdn & !_psen & !a15)
# (!pdn & UPDATA & !pgr2 & !pgr1 & !pgr0 & !a15);
fs1 = (!pdn & !_psen & !pgr2 & !pgr1 & !pgr0 & a15)
# (!pdn & UPDATA & !pgr2 & !pgr1 & pgr0 & !a15);
fs2 = (!pdn & !_psen & !pgr2 & !pgr1 & pgr0 & a15)
# (!pdn & UPDATA & !pgr2 & pgr1 & !pgr0 & !a15);
fs3 = (!pdn & !_psen & !pgr2 & pgr1 & !pgr0 & a15)
# (!pdn & UPDATA & !pgr2 & pgr1 & pgr0 & !a15);
fs4 = (!pdn & !_psen & !pgr2 & pgr1 & pgr0 & a15)
# (!pdn & UPDATA & pgr2 & !pgr1 & !pgr0 & !a15);
fs5 = (!pdn & !_psen & pgr2 & !pgr1 & !pgr0 & a15)
# (!pdn & UPDATA & pgr2 & !pgr1 & pgr0 & !a15);
fs6 = (!pdn & !_psen & pgr2 & !pgr1 & pgr0 & a15)
# (!pdn & UPDATA & pgr2 & pgr1 & !pgr0 & !a15);
fs7 = (!pdn & !_psen & pgr2 & pgr1 & !pgr0 & a15)
# (!pdn & UPDATA & pgr2 & pgr1 & pgr0 & !a15);
csboot0 = !pdn & !_psen & !a15 & !a14 & !a13;
csboot1 = !pdn & !_psen & !a15 & !a14 & a13;
csboot2 = !pdn & !_psen & !a15 & a14 & !a13;
csboot3 = !pdn & !_psen & !a15 & a14 & a13;
csiop = !pdn & a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & !a8;
rs0 = rs0_0.FB;
jtagsel = !_reset;
PORTA EQUATIONS :
=======================
CNT1.D := CNT0.Q & !CNT1.Q;
CNT1.PR = 0;
CNT1.RE = 0;
CNT1.C = !clkcard;
clkcard.LE = 1;
simclk = !CNT2.Q;
simclk.OE = 1;
smclk = !CNT2.Q;
smclk.OE = 1;
AD12 = a12;
AD12.OE = 1;
AD13 = a13;
AD13.OE = 1;
AD14 = a14;
AD14.OE = 1;
PT_le = !_wr & PGR6 & a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a7 & !a6 & !a5 & a4 & !a3 & !a2 & a1 & !a0;
PT_le.OE = 1;
CNT0.D := !CNT0.Q & !CNT1.Q;
CNT0.PR = 0;
CNT0.RE = 0;
CNT0.C = !clkcard;
PORTB EQUATIONS :
=======================
VFD_DO.OE = 1;
VFD_SCK.OE = 1;
VFD_STB.OE = 1;
K_DI.OE = 1;
CS1 = !_wr & PGR6 & a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a7 & !a6 & !a5 & a4 & !a3 & !a2 & a1 & a0;
CS1.OE = 1;
!rd_cpld = PGR6 & a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a7 & !a6 & !a5 & a4 & !a3 & !a2 & !a1 & !a0;
rd_cpld.OE = 1;
PORTC EQUATIONS :
=======================
CNT2.D := CNT1.Q & !CNT2.Q;
CNT2.PR = 0;
CNT2.RE = 0;
CNT2.C = CNT1.Q;
!rs0_0 = (!a15)
# (!a14 & !a13 & !a12 & !a11 & !a10 & !a9)
# (pdn);
!CSPLD = a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a7 & !a6 & !a5 & !a4 & !a3;
CSPLD.OE = 1;
!SRAMCS = (!_wr & SRAM & !a15)
# (!_rd & SRAM & !a15);
SRAMCS.OE = 1;
!CEFS = (!_wr & FLSAH & !a15)
# (!_rd & FLSAH & !a15);
CEFS.OE = 1;
PORTD EQUATIONS :
=======================
!USB_CS = PGR6 & a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a7 & !a6 & !a5 & a4 & !a3 & a2 & !a1 & a0;
USB_CS.OE = 1;
--- End ---
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