代码搜索：codein
找到约 22 项符合「codein」的源代码
代码结果 22
www.eeworm.com/read/188244/8555370
v testbench.v
`timescale 1ns/1ns
module testbench;
reg clk;
reg rst;
reg codein;
wire [1:0] codeoutv;
wire [1:0] codeoutb;
initial
begin
clk
www.eeworm.com/read/188244/8555384
bak testbench.v.bak
`timescale 1ns/1ns
module testbench;
reg clk;
reg rst;
reg codein;
wire [1:0] codeoutv;
wire [1:0] codeoutb;
initial
begin
clk
www.eeworm.com/read/395983/8138620
cls cothercode.cls
VERSION 1.0 CLASS
BEGIN
MultiUse = -1 'True
Persistable = 0 'NotPersistable
DataBindingBehavior = 0 'vbNone
DataSourceBehavior = 0 'vbNone
MTSTransactionMode = 0 'NotAnMTSObject
www.eeworm.com/read/337844/12336970
cpp 1009_smh.cpp
#include
#include
class coder {
public :void ini(int m,char a[]);
void reini();
void rotate();
int codein(int out);
int oneround();
int codeout(int in);
private:
int a
www.eeworm.com/read/203573/15355535
m decode_spiht.m
function A=decode_SPIHT(Linein,Linelength,Tin,ALR)
if nargin==0
line1='10110011000010000001010100000';
line2='11100000000000000001010';
line3='10101110101100001011111011010001000100010
www.eeworm.com/read/295958/8131342
vhd hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
codeout: out std_logic_vector(1 downto 0));
end;
ar
www.eeworm.com/read/312826/13603741
vhd hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
codeout: out std_logic_vector(1 downto 0));
end hd
www.eeworm.com/read/310640/13648031
hier_info weifenqi.hier_info
|weifenqi
codeout inst1.IN0
codein => inst.IN0
codein => yicunqi:inst5.Din
clkin => yicunqi:inst5.clk
|weifenqi|yicunqi:inst5
Dout
www.eeworm.com/read/385348/8808272
cpp 词法分析dlg.cpp
// 词法分析Dlg.cpp : implementation file
//
#include "stdafx.h"
#include "词法分析.h"
#include "词法分析Dlg.h"
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] = __FILE__;
www.eeworm.com/read/464953/7063740
hier_info hdb3.hier_info
|HDB3
HDB3[0] insertb:inst1.clk
CLK => insertv:inst.clk
CLR => insertv:inst.clr
datain => insertv:inst.