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找到约 3,833 项符合「bench」的源代码

代码结果 3,833
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/345878/3196068

s timer.s

.file "c:/at91/software/projects/bench/source/timer.c" .option svr4 .option thumb_code .option inter .ident "hc4.5a -O7 \n" .option noswst .seg ".text",text .option code16,inter .L00TE
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www.eeworm.com/read/345878/3196069

s com.s

.file "c:/at91/software/projects/bench/source/com.c" .option svr4 .option thumb_code .option inter .ident "hc4.5a -O7 \n" .option noswst .seg ".text",text .option code16,inter .L00TEXT
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www.eeworm.com/read/343627/3218952

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
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www.eeworm.com/read/326939/3465671

make

verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_
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www.eeworm.com/read/316247/3612471

make

verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_
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www.eeworm.com/read/405803/2282961

make

verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_
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www.eeworm.com/read/405803/2283019

make

verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_
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www.eeworm.com/read/154076/5643171

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
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www.eeworm.com/read/235010/14088995

ant test_ddr_command.ant

// F:\ISE_TEST // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Tue Aug 14 10:56:43 2007 `timescale 1ns/1ns `define FDEPTH 4 `define C_READ 5 `define D 10 `define IF2 3
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www.eeworm.com/read/137348/13327244

make

../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ..
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