代码搜索：asynchronous
找到约 2,366 项符合「asynchronous」的源代码
代码结果 2,366
www.eeworm.com/read/101082/6246493
8nfs biod.8nfs
.\" SCCSID: @(#)biod.8nfs 8.1 9/11/90
.TH biod 8nfs
.SH Name
biod \- Start NFS asynchronous block I/O daemons
.SH Syntax
.nf
.ft B
.B /etc/biod [\fIndaemons\fP]
.fi
.SH Description
.NXR "biod daemon"
www.eeworm.com/read/382666/6286504
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/494695/6360565
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/487908/6501844
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/481375/6639517
h initialization.h
void AVR_Initialize()
{
PORTA=0x00; PORTB=0x00; PORTC=0x00; PORTD=0x00;
DDRA=0x00; DDRB=0xB0; DDRC=0x00; DDRD=0x00;
www.eeworm.com/read/263314/11367751
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/406292/11444985
v dram.v
// picdram stands for PIC "Data" RAM.
//
//
// Synchronous Data RAM, 8 bits wide, N words deep.
//
// ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs **
// This is so that we can do a Rea
www.eeworm.com/read/157785/11663020
v mult4x4_s.v
//
// Module: MULT4X4_S
//
// Description: Verilog Sub-module
// 4-bit X 4-bit embedded signed multiplier (asynchronous)
//
// Device: Virtex-II Family
//
// Copyright (c) 2000 Xilinx, Inc. A
www.eeworm.com/read/157785/11663023
v signed_mult_18x18.v
//
// Module: SIGNED_MULT_18X18
//
// Description: Verilog instantiation template
// 18-bit X 18-bit embedded signed multiplier (asynchronous)
//
// Device: Virtex-II Family
//
// Copyright (c
www.eeworm.com/read/157785/11663027
v mult4x4_u.v
//
// Module: MULT4X4_U
//
// Description: Verilog Sub-module
// 4-bit X 4-bit embedded unsigned multiplier (asynchronous)
//
// Device: Virtex-II Family
//
// Copyright (c) 2000 Xilinx, Inc.