代码搜索:asynchronous

找到约 2,366 项符合「asynchronous」的源代码

代码结果 2,366
www.eeworm.com/read/179087/9373480

3_08bcu

//---------------------------------------------------------------------------- g0000 // g0001 // BCU: module for bus c
www.eeworm.com/read/178672/9389062

vhd reginf.vhd

-- MAX+plus II VHDL Example -- Register Inference -- Copyright (c) 1994 Altera Corporation ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2, q3, q4, q5, q6, q7 : O
www.eeworm.com/read/178074/9419127

v dram.v

// picdram stands for PIC "Data" RAM. // // // Synchronous Data RAM, 8 bits wide, N words deep. // // ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs ** // This is so that we can do a Rea
www.eeworm.com/read/372855/9489518

v dram.v

// picdram stands for PIC "Data" RAM. // // // Synchronous Data RAM, 8 bits wide, N words deep. // // ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs ** // This is so that we can do a Rea
www.eeworm.com/read/363059/9969445

h async.h

/*0001*//* /*0002./ * Copyright (c) 1998-2001 Sun Microsystems, Inc. All Rights Reserved. /*0003./ * /*0004./ * This software is the confidential and proprietary information of Sun /*0005./ * Micr
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vhd reginf.vhd

-- MAX+plus II VHDL Example -- Register Inference -- Copyright (c) 1994 Altera Corporation Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load
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vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
www.eeworm.com/read/161056/10458346

v dram.v

// picdram stands for PIC "Data" RAM. // // // Synchronous Data RAM, 8 bits wide, N words deep. // // ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs ** // This is so that we can do a Rea
www.eeworm.com/read/422532/10631529

vhd reginf.vhd

-- MAX+plus II VHDL Example -- Register Inference -- Copyright (c) 1994 Altera Corporation ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2, q3, q4, q5, q6, q7 : O
www.eeworm.com/read/159105/10694452

vhd reginf.vhd

-- MAX+plus II VHDL Example -- Register Inference -- Copyright (c) 1994 Altera Corporation ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2, q3, q4, q5, q6, q7 : O