3_08bcu

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   g0000
//                                                                               g0001
// BCU: module for bus control unit                                              g0002
//                                                                               g0003
// The BCU adapts the internal data and address buses of                         g0004
// IFU and MAU to the external ones. The PCU controls bus                        g0005
// allocation by BCU_ACC_MODE and BCU_ACC_DIR. At the                            g0006
// beginning of a memory access, informations are valid                          g0007
// due to the nMRQ delay 'BCUDELAY, which has to be chosen                       g0008
// greater than register transfer delay 'DELTA.                                  g0009
// An asynchronous as well as a synchronous protocol                             g0010
// may be selected for memory accesses by BUS_PRO.                               g0011
//                                                                               g0012
//                                                                               g0013
// Signal encodings:                                                             g0014
// ACMD:             00: byte access                                             g0015
//                   01: halfword access                                         g0016
//                   10: word access                                             g0017
//                   11: RESET                                                   g0018
// BCU_ACC_MODE:    000: MAU byte access                                         g0019
//                  001: MAU halfword access                                     g0020
//                  010: MAU word access                                         g0021
//                  110: IFU fetch access                                        g0022
// BCU_ACC_DIR:      00: read data                                               g0023
//                   01: write data                                              g0024
//                   10: swap data                                               g0025
// BUS_PRO:           0: asynchronous memory access protocol                     g0026
//                    1: synchronous memory access protocol                      g0027
//                                                                               g0028
//----------------------------------------------------------------------------   g0029
                                                                                 g0030
module bcu (                                                                     g0031
    MAU_READ_DATA, IFU_DATA_BUS,                                                 g0032
    ADDR_BUS,                                                                    g0033
    ACMD, BCU_READY, nMRQ, FACC, nRMW, RnW,                                      g0034
    DATA_BUS,                                                                    g0035
    MAU_WRITE_DATA,                                                              g0036
    IFU_ADDR_BUS, MAU_ADDR_BUS,                                                  g0037
    CP, nRESET, BCU_ACC_MODE, BCU_ACC_DIR, BREAK_MEM_ACC, DO_FETCH,              g0038
    BUS_PRO, nHLT, nMHS                                                          g0039
  );                                                                             g0040
                                                                                 g0041
  // Outputs                                                                     g0042
  output [31:0] MAU_READ_DATA;  // read data for MAU                             g0043
  output [31:0] IFU_DATA_BUS;   // memory word fetched for IFU                   g0044
  output [31:0] ADDR_BUS;       // address bus                                   g0045
  output [1:0]  ACMD;           // access width                                  g0046
  output        BCU_READY;      // BCU ready                                     g0047
  output        nMRQ;           // memory request                                g0048
  output        FACC;           // fetch access                                  g0049
  output        nRMW;           // read modify write cycle                       g0050
  output        RnW;            // read/write access                             g0051
                                                                                 g0052
  // Bidirectional                                                               g0053
  inout  [31:0] DATA_BUS;       // data bus                                      g0054
                                                                                 g0055
  // Inputs                                                                      g0056
  input  [31:0] MAU_WRITE_DATA; // write data from MAU                           g0057
  input  [31:2] IFU_ADDR_BUS;   // fetch address from IFU ( = PC_BUS)            g0058
  input  [31:0] MAU_ADDR_BUS;   // address for MAU access                        g0059
  input         CP;             // system clock                                  g0060
  input         nRESET;         // reset                                         g0061
  input  [2:0]  BCU_ACC_MODE;   // access mode                                   g0062
  input  [1:0]  BCU_ACC_DIR;    // read, swap, or write                          g0063
  input         BREAK_MEM_ACC;  // break memory access                           g0064
  input         DO_FETCH;       // fetch                                         g0065
  input         BUS_PRO;        // select bus protocol                           g0066
  input         nHLT;           // external halt                                 g0067
  input         nMHS;           // memory handshake                              g0068
                                                                                 g0069
  wire   [31:0] MAU_READ_DATA;  // read data for MAU                             g0070
  wire   [31:0] IFU_DATA_BUS;   // memory word fetched for IFU                   g0071
  wire   [31:0] ADDR_BUS;       // address bus                                   g0072
  wire   [1:0]  ACMD;           // access width                                  g0073
  wire          BCU_READY;      // BCU ready                                     g0074
  wire          FACC;           // fetch access                                  g0075
  wire          nMRQ;           // memory request                                g0076
  wire          nRMW;           // read modify write cycle                       g0077
  wire          RnW;            // read/write access                             g0078
                                                                                 g0079
  wire   [31:0] DATA_BUS;       // data bus                                      g0080
                                                                                 g0081
  wire   [31:0] MAU_WRITE_DATA; // write data from MAU                           g0082
  wire   [31:2] IFU_ADDR_BUS;   // fetch address from IFU                        g0083
  wire   [31:0] MAU_ADDR_BUS;   // address for MAU access                        g0084
  wire          CP;             // system clock                                  g0085
  wire          nRESET;         // reset                                         g0086
  wire   [2:0]  BCU_ACC_MODE;   // access mode                                   g0087
  wire   [1:0]  BCU_ACC_DIR;    // read, swap, or write                          g0088
  wire          BREAK_MEM_ACC;  // break memory access                           g0089
  wire          DO_FETCH;       // fetch                                         g0090
  wire          BUS_PRO;        // select bus protocol                           g0091
  wire          nHLT;           // external halt                                 g0092
  wire          nMHS;           // memory handshake                              g0093
                                                                                 g0094
  // Internal registers                                                          g0095
  reg    [31:0] READ_BUFFER;    // input latch of data bus                       g0096
  reg    [31:0] ADDR_DRV;       // tri-state driver for address bus              g0097
  reg    [31:0] DATA_DRV;       // tri-state driver for data bus                 g0098
  reg    [ 2:0] ACC_MODE;       // BCU_ACC_MODE                                  g0099
  reg           ABP_ADDE;       // enable address bus driver (asynchronous)      g0100
  reg           ABP_BUSY;       // memory access in progress (asynchronous)      g0101
  reg           ABP_DADE;       // enable data bus driver (asynchronous)         g0102
  reg           ABP_READ;       // take data (asynchronous)                      g0103
  reg           ABP_RnW;        // read / not write (asynchronous)               g0104
  reg           ABP_nMRQ;       // memory request (asynchronous)                 g0105
  reg           ABP_nRMW;       // read modify write (asynchronous)              g0106
  reg           SBP_ADDE;       // enable address bus driver (synchronous)       g0107
  reg           SBP_BUSY;       // memory access in progress (synchronous)       g0108
  reg           SBP_DADE;       // enable data bus driver (synchronous)          g0109
  reg           SBP_READ;       // take data (synchronous)                       g0110
  reg           SBP_RnW;        // read / not write (synchronous)                g0111
  reg           SBP_SWAP;       // first swap cycle (synchronous)                g0112
  reg           SBP_nMRQ;       // memory request (synchronous)                  g0113
  reg           SBP_nRMW;       // read modify write (synchronous)               g0114
                                                                                 g0115
  // Continuous assignments                                                      g0116
  assign IFU_DATA_BUS  = READ_BUFFER;    // read data for IFU                    g0117
  assign MAU_READ_DATA = READ_BUFFER;    // read data for MAU                    g0118
  assign ADDR_BUS = ADDR_DRV;            // address bus                          g0119
  assign DATA_BUS = DATA_DRV;            // data bus                             g0120
  assign FACC = ACC_MODE[2];             // fetch access                         g0121
  assign ACMD = ACC_MODE[1:0];           // access width                         g0122
  assign BCU_READY = (BUS_PRO) ? (~SBP_BUSY & nHLT) : (~ABP_BUSY & nHLT);        g0123
  assign RnW       = (BUS_PRO) ? (SBP_RnW)          : (ABP_RnW);                 g0124
  assign nMRQ      = (BUS_PRO) ? (SBP_nMRQ)         : (ABP_nMRQ);                g0125
  assign nRMW      = (BUS_PRO) ? (SBP_nRMW)         : (ABP_nRMW);                g0126
                                                                                 g0127