代码搜索：asynchronous
找到约 2,366 项符合「asynchronous」的源代码
代码结果 2,366
www.eeworm.com/read/120487/6073372
c testlibpq2.c
/*
* testlibpq2.c
* Test of the asynchronous notification interface
*
* Start this program, then from psql in another window do
* NOTIFY TBL2;
* Repeat four times to get this program to exit.
www.eeworm.com/read/110034/6170609
c x25_asy.c
/*
* Things to sort out:
*
* o tbusy handling
* o allow users to set the parameters
* o sync/async switching ?
*
* Note: This does _not_ implement CCITT X.25 asynchronous framing
* recommendat
www.eeworm.com/read/102935/6229418
c x25_asy.c
/*
* Things to sort out:
*
* o tbusy handling
* o allow users to set the parameters
* o sync/async switching ?
*
* Note: This does _not_ implement CCITT X.25 asynchronous framing
* recommendat
www.eeworm.com/read/214887/6294646
v cntr_struct.v
// D flipflop with positive edge clock and
// high asynchronous reset
module dff (d, rst, clk, q);
input d;
input rst;
input clk;
output q;
reg q;
// events of interest are
www.eeworm.com/read/486068/6542897
vhd uart.vhd
-- EE301B Semester Project, Winter 1998
-- 8051 UART (Universal Asynchronous Receiver/Transmitter) model
-- Source : Intel 8051 Family Microprocessors Manual
-- Author : Lingfeng Yuan, Prajakta Kurv
www.eeworm.com/read/341658/12074400
vhd ascount.vhd
-- Synchronous Counter of Generic Size
--
-- Countersize--size of counter
--
-- clk--posedge clock input
-- areset--asynchronous reset
-- sreset--active high input resets counter to 0
-- enable
www.eeworm.com/read/151714/12179488
vhd t80a.vhd
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redist
www.eeworm.com/read/210282/15202262
v jpeg_yuce.v
module jpeg_yuce(clk, rst, din, i, dcpm);
input clk; // system clock
input rst; // asynchronous reset
//input ena; // clock enable
input [0:23] din; // data
www.eeworm.com/read/206514/15294061
v cntr_struct.v
// D flipflop with positive edge clock and
// high asynchronous reset
module dff (d, rst, clk, q);
input d;
input rst;
input clk;
output q;
reg q;
// events of interest are
www.eeworm.com/read/18528/793177
v cntr_struct.v
// D flipflop with positive edge clock and
// high asynchronous reset
module dff (d, rst, clk, q);
input d;
input rst;
input clk;
output q;
reg q;
// events of interest are