jpeg_yuce.v

预测编码dpcm 的verilog代码

module jpeg_yuce(clk, rst, din, i, dcpm);
	input         clk;     // system clock
	input         rst;    // asynchronous reset
	//input         ena;     // clock enable
	input  [0:23] din;     // data input
   output i;
	output [0:23] dcpm;
	integer i;
	wire [0:23] dcpm;
	reg [0:7] tempR;
	reg [0:7] tempG;
	reg [0:7] tempB;
	reg [0:7] tempR1;
	reg [0:7] tempB1;
	reg [0:7] tempG1;
	reg [0:7] dcpmR;
	reg [0:7] dcpmG;
	reg [0:7] dcpmB;
	reg [0:7] Dram[1:1024];
	integer j,k;
	parameter width=10'd5,length=10'd20;
	task Panduan;
 	  input tempX1;
 	  output tempX;
	  if(tempX1<0)
	    tempX=0;
	  else 
	    if(tempX1>255)
	      tempX=255;
	    else
	      tempX=tempX1;
	endtask

	always @(posedge clk or negedge rst)
	begin
	  if(!rst)
	    begin
	        i<=1;
	        j<=2;
	        k<=3;
	        {dcpmR,dcpmG,dcpmB}<=24'b0000_0000_0000_0000_0000_0000;
	    end
	  else
	  	 if(i<=1024)
	    begin
	        {Dram[i],Dram[i+1],Dram[i+2]}<=din;
	        i<=i+3;
	        j<=i+4;
	        k<=i+5;
	    if(i==1)
	    begin
   	       dcpmR<=din[0:7];
	        dcpmG<=din[8:15];
	        dcpmB<=din[9:23];
	        end
	    else 
	    if(i<16)
	      begin
   	       dcpmR<=din[0:7]-Dram[i-3];
	        dcpmG<=din[8:15]-Dram[j-3];
	        dcpmB<=din[16:23]-Dram[k-3];
	      end
	    else 
	    if((i-1)%15==0)
	        begin
	          dcpmR<=din[0:7]-Dram[i-15];
	          dcpmG<=din[8:15]-Dram[j-15];
	          dcpmB<=din[16:23]-Dram[k-15];
	        end
	    else
	        begin
             tempR1=(Dram[i-15]-Dram[i-18])/2+Dram[i-3];
       	     tempB1=(Dram[j-15]-Dram[j-18])/2+Dram[j-3];
 	     	    tempG1=(Dram[k-15]-Dram[k-18])/2+Dram[k-3];
 	     	    Panduan(tempR1,tempR);
 	     	    Panduan(tempB1,tempB);
 	     	    Panduan(tempG1,tempG);
	          dcpmR=din[0:7]-tempR;
	          dcpmG=din[8:15]-tempG;
	          dcpmB=din[16:23]-tempB;
	        end
	        end
	 end  
assign dcpm={dcpmR,dcpmG,dcpmB};
endmodule