代码搜索：adder4
找到约 194 项符合「adder4」的源代码
代码结果 194
www.eeworm.com/read/214503/15098214
lfp adder4.lfp
# begin LFP file F:\XilinxLab\myfirst\adder\adder4.lfp
designfile adder4.ngd
IO_GROUP "sum" IO_GROUP="adder4" ;
IO_GROUP "inb" IO_GROUP="adder4" ;
IO_GROUP "ina" IO_GROUP="adder4" ;
INST "adder4"
www.eeworm.com/read/415793/11053787
vhd adder4.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD_LOGIC ;
s3, s2, s1, s0 : OU
www.eeworm.com/read/119738/14823276
vhd adder4.vhd
-- This VHDL Source Have been create with WITHCLASS95
-- Scrip file written by Clerbois M
package ADDER4PKG is
COMPONENT ADDER4
PORT (
-- CLOCK,RESET:IN BIT; only for synchronous objec
www.eeworm.com/read/252132/12300554
vhd adder4.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD
www.eeworm.com/read/368409/9697006
v bcdadder4.v
//------------------------------------
//4-bit BCD adder
//Filename : BCDadder4.v
//------------------------------------
module BCDadder4(S, Cout, Cin, A, B);
output [3:0] S; //Sumation output
o
www.eeworm.com/read/415793/11053811
vhd adder4.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD
www.eeworm.com/read/409342/11332186
rpt adder4.flow.rpt
Flow report for adder4
Sat Nov 15 23:25:17 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
www.eeworm.com/read/252132/12300538
vhd adder4.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOG
www.eeworm.com/read/415793/11053793
vhd adder4.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOG
www.eeworm.com/read/468753/6987431
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity adder4 is
port(
s : out vl_logic_vector(3 downto 0);
co : out vl_logic;
a :