代码搜索：adder
找到约 6,792 项符合「adder」的源代码
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www.eeworm.com/read/461590/7223942
doc fp_adder.doc
-------------------------------------------------------------------------------
--
-- Floating Point Adder/Subtractor Benchmark: Main File Documentation
--
-- Source: Patterson, David A., and Henness
www.eeworm.com/read/461262/7230931
v adder1.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:50:44 09/09/2007
// Design Name:
// Modul
www.eeworm.com/read/461262/7230972
xco aa_adder.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/461262/7231020
v adder8.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:44 10/08/2007
// Design Name:
/
www.eeworm.com/read/460642/7244574
bsf half_adder.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/460642/7244575
vhd half_adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity half_adder is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC
);
end half_ad
www.eeworm.com/read/460642/7244576
qws full_adder.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
[ProjectWorkspace.Frames.
www.eeworm.com/read/460642/7244580
vwf half_adder.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/460642/7244582
qsf full_adder.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/460642/7244583
bdf full_adder.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to