代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/454493/7388275
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/436587/7767159
summary half_ad.fit.summary
Fitter Status : Successful - Mon Mar 23 16:17:16 2009
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : half_ad
Top-level Entity Name : adder_4
Family : Cyclone
Device
www.eeworm.com/read/436587/7767178
summary half_ad.map.summary
Analysis & Synthesis Status : Successful - Mon Mar 23 16:17:08 2009
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : half_ad
Top-level Entity Name : adder_4
Family : C
www.eeworm.com/read/435744/7785923
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/240876/13189714
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/325597/13194959
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/138605/13228519
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/310741/13644706
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/306208/13749241
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/13816/283912
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆