代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/385917/8781917
vhd fa.vhd
--bypass adder 子单元
library ieee;
use ieee.std_logic_1164.all;
entity Fa is
port (Pi,Gi,Ci:in std_logic;
Coi,Si:out std_logic
);
end Fa;
architecture Fabehav of Fa is
begin
Coi
www.eeworm.com/read/382603/9017019
v fft.v
module sequential__adder(a, b, sum, clock);
parameter width = 1;
input [width-1:0] a;
input [width-1:0] b;
input clock;
output [width-1:0] sum;
reg [width-1:0] sum;
always @(posedge
www.eeworm.com/read/158979/10705723
cpp 3sat 问题.cpp
// 3SAT
#include
#include
#include
#include
const unsigned long maxshort=65536L;
const unsigned long multiplier=1194211693L;
const unsigned long adder
www.eeworm.com/read/467448/7012951
hif dds.hif
Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1595
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
adder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
#
www.eeworm.com/read/216450/4894206
makefile
# Makefile for lib/float.
CC1 = /bin/sh ./FP.compile
LIBRARY = ../libfp.a
all: $(LIBRARY)
OBJECTS = \
$(LIBRARY)(add_ext.o) \
$(LIBRARY)(adder.o) \
$(LIBRARY)(adf4.o) \
$(LIBRARY)(adf8.o) \
$(
www.eeworm.com/read/377553/9271612
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/178844/9383945
c jmq.c
#include
#include
#include
#include
#define uchar unsigned char
#define uint unsigned int
#define ulong unsigned long
#define adder 0x83
//#define BN 8
/
www.eeworm.com/read/164942/10081156
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/275690/10800944
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/274276/10879320
vhd fadd4.vhd
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
a : in std_logic_vector(3 downto 0);--砆