代码搜索:adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
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h randnumber.h

#include "time.h" //used to generate a random number from the current seed const unsigned long maxshort=65536L; const unsigned long multiplier=1194211693L; const unsigned long adder=12345L; c
www.eeworm.com/read/366924/2858034

h randnumber.h

#include "time.h" //used to generate a random number from the current seed const unsigned long maxshort=65536L; const unsigned long multiplier=1194211693L; const unsigned long adder=12345L; c
www.eeworm.com/read/360977/2954507

h randnumber.h

#include "time.h" //used to generate a random number from the current seed const unsigned long maxshort=65536L; const unsigned long multiplier=1194211693L; const unsigned long adder=12345L; c
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vhd bcd.vhd

--bcd.vhd 1 digits bcd adder/subtractor library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity bcd is port( a : in std_logic_vector(3 downto 0);--砆
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asp toplist.asp

www.eeworm.com/read/101839/15801991

asp toplist.asp

www.eeworm.com/read/420216/10810520

h constant.h

#define uchar unsigned char #define uint unsigned int #define FALSE 1 #define TRUE 0 #define LED_TIMER -3096 ioport unsigned int port8002; #define LED_ADDER port8002 ioport unsig
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scr initial_compile.scr

/* Initial compile with estimate/time budget constraints */ include script_path + read.scr current_design ChipLevel include script_path + defaults.con include script_path + adder16.scr include scri
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transcript

# Reading E:/ModelSim/win32/../tcl/vsim/pref.tcl # vsim {E:\EDA} {DownLoad\Verilog\source\chap3\adder4.v} # ERROR: Could not open library work at work: No such file or directory # ERROR: Could no
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vhd addn.vhd

-- n-bit Adder using the Generate Statement -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY addn IS GENERIC(n : POSITIVE := 3); -