代码搜索:adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
www.eeworm.com/read/264079/11330328

out b.v.out

www.eeworm.com/read/264079/11330341

out d.v.out

www.eeworm.com/read/264079/11330343

out c.v.out

www.eeworm.com/read/264079/11330374

out test.tcl.out

www.eeworm.com/read/264079/11330390

out test.tcl.out

www.eeworm.com/read/341850/12057960

tdf bitadd.tdf

% Serial adder - inspired by the work of Ray Andraka Written by steven groom (steven.groom@arrow.co.nz) This module can be used freely as and when needed as long as this message remains intact.
www.eeworm.com/read/13816/283916

vhd fadd.vhd

--fadd.vhd fadd.vhd one bit full adder library ieee ; use ieee.std_logic_1164.all; entity fadd is port( a: in std_logic;--砆
www.eeworm.com/read/18335/784538

v pad.v

// This example shows one how to force the // use of a particular pad type for lucent. module adder(cout, sum, a, b, cin); parameter size = 1; /* declare a parameter. default required */ outpu
www.eeworm.com/read/478903/1348170

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity adder is port( a : in vl_logic_vector(3 downto 0); b : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/325655/3481177

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity adder is port( a : in vl_logic_vector(3 downto 0); b : in vl_logic_vector(3 downto 0);