代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/370927/9574961
vhd full_adder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pkg_Full_Adder.all;
entity Full_Adder is
port( in1 : in std_logic;
in2 : in std_logic
www.eeworm.com/read/170129/9818099
vhd adder4.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
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vhd 2_adder.vhd
entity adder is
port (
in1 : bit_vector;
in2 : bit_vector;
pout : out bit_vector
);
end adder;
architecture func of adder is
begin
process(in1,in2)
begin
pout
www.eeworm.com/read/366181/9826259
vhd 1_adder.vhd
entity bit_rtl_adder is
port (
in1 : bit_vector;
in2 : bit_vector;
cntl : bit;
pout : out bit_vector
);
end bit_rtl_adder;
architecture func of bit_rtl_adder is
begin
www.eeworm.com/read/169221/9874951
v adder16.v
`include "adder.v"
module adder16(cout,sum,a,b,cin);
output cout;
parameter my_size=16;
output[my_size-1:0] sum;
input[my_size-1:0] a,b;
input cin;
adder my_adder(cout,sum,a,b,cin);
endmod
www.eeworm.com/read/169221/9875108
v adder8.v
module adder8(cout,sum,ina,inb,cin,clk);
output[7:0] sum;
output cout;
input[7:0] ina,inb;
input cin,clk;
reg[7:0] tempa,tempb,sum;
reg cout;
reg tempc;
always @(posedge clk)
begin
tempa=i
www.eeworm.com/read/169221/9875142
acf adder4.acf
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
www.eeworm.com/read/169221/9875146
v adder4.v
module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;
input[3:0] ina,inb;
input cin;
assign {cout,sum}=ina+inb+cin;
endmodule
www.eeworm.com/read/169221/9875149
ndb adder4.ndb
NDB006
The number of symbol table entries is: 1
The length of the symbol table is: 2
Index Hierarchy Path
----- --------------
! |
The number of name info structs is : 1
InsOrder BitField
www.eeworm.com/read/169221/9875151
v adder_tp.v
`timescale 1ns/1ns
`include "adder4.v"
module adder_tp;
reg[3:0] a,b;
reg cin;
wire[3:0] sum;
wire cout;
integer i,j;
adder4 adder(sum,cout,a,b,cin);
always #5 cin=~cin;
initial
begin