代码搜索:adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
www.eeworm.com/read/323586/13334732

rpt clock.sim.rpt

Simulator report for clock Thu Jun 05 09:19:24 2008 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
www.eeworm.com/read/323333/13343700

fit cpld_dsp.fit

-- MAX+plus II Compiler Fit File -- Version 10.2 07/10/2002 -- Compiled: 03/07/2008 11:43:44 -- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and
www.eeworm.com/read/313300/13590621

vho _8bitfulladd.vho

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
www.eeworm.com/read/308964/13685624

fit multi.fit

-- MAX+plus II Compiler Fit File -- Version 10.2 07/10/2002 -- Compiled: 01/08/2007 20:53:15 -- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and
www.eeworm.com/read/308964/13685740

hif mytest.hif

HIF003 -- -- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, an
www.eeworm.com/read/308960/13686365

fit multi.fit

-- MAX+plus II Compiler Fit File -- Version 10.2 07/10/2002 -- Compiled: 01/08/2007 20:53:15 -- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and
www.eeworm.com/read/132821/5909223

el mult.el

(progn (load "../g1") (load "../l1") (load "../b1") (load "m1") (load "c1") (load "compressor") (load "components") (setq b 128) (setq w 4) (setq h (gen-tree b w ))
www.eeworm.com/read/482411/6624318

vo huang.vo

// Copyright (C) 1991-2006 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any o
www.eeworm.com/read/480425/6663963

hier_info dds.hier_info

|dds SYSCLK => sync_fcw[21].CLK SYSCLK => sync_fcw[20].CLK SYSCLK => sync_fcw[19].CLK SYSCLK => sync_fcw[18].CLK SYSCLK => sync_fcw[17].CLK SYSCLK => sync_fcw[16].CLK SYSCLK => sync_fcw[15].CLK
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txt readme.txt

下载程序:ADDER4.SOF 开关设置:JP1 插上K1-K8,K9-K16,L9-L16 操作运行:k1-k4分别对应输入二进制数A的高位到低位; K5-K8分别对应输入二进制数B的高位到低位; K9对应加法器的进位; L15-L12分别对应显示输出和SUM的高位到低位; L16显