代码搜索：aRM
找到约 10,000 项符合「aRM」的源代码
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www.eeworm.com/read/308751/13693516
udo arm.udo
-- ProjNav VHDL simulation template: arm.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/308751/13693612
ant arm.ant
// E:\ISE6.1\TST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Sun May 06 09:28:57 2007
`timescale 1ns/1ns
`define F_ASSERT 2
`define s3 3
`define N 5
`define IF1 2
`
www.eeworm.com/read/308751/13693669
tfw arm.tfw
// E:\ISE6.1\TST
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Sun May 06 09:28:57 2007
//
// Notes:
// 1) This test fixture has been automatically generated from
// your Test Be
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fdo arm.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun May 06 09:28:58 中国标准时间 2007
##
vlib work
vlog my_dcm1.v
vlog rom.v
vlog armtst.v
vlog arm.tfw
vlog C:/Xi
www.eeworm.com/read/308751/13693830
tbw arm.tbw
www.eeworm.com/read/307507/13720921
scatter arm.scatter
LOAD_ROM 0x0000000
{
ER_INIT 0x0c00000
{
Init (+RO)
}
ER_ROM +0
{
.ANY(+RO)
}
DATABLACK
{
RamData (
www.eeworm.com/read/305275/13775942
mcp arm.mcp
www.eeworm.com/read/305275/13775944
axf arm.axf
www.eeworm.com/read/305275/13775949
bin arm.bin
www.eeworm.com/read/302447/13834860