代码搜索：XAPP
找到约 1,517 项符合「XAPP」的源代码
代码结果 1,517
www.eeworm.com/read/272638/10951281
pjt fuction.pjt
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectDir="D:\DM64xApp\fuction\"
ProjectType=Library
CPUFamily=TMS320C64XX
Tool="Archiver"
Too
www.eeworm.com/read/458392/7297298
m transformpathfromnu.m
function [alphamat,alpha0vec,lambdavec,nuvec]=TransformPathFromNu(alphamat,alpha0vec,lambdavec,nuvec,Nbapp);
N=length(nuvec);
%Nbapp=size(xapp,1);
%nuvec=fliplr(linspace(min(lambdavec)/Nbapp,max(
www.eeworm.com/read/398337/7993877
m transformpathfromnu.m
function [alphamat,alpha0vec,lambdavec,nuvec]=TransformPathFromNu(alphamat,alpha0vec,lambdavec,nuvec,Nbapp);
N=length(nuvec);
%Nbapp=size(xapp,1);
%nuvec=fliplr(linspace(min(lambdavec)/Nbapp,max(
www.eeworm.com/read/237345/6321855
txt readme.txt
XAPP610 Zip file contains
The word document for DCT
Verilog files (*.v)
dct.v
test_dct.v
Vhdl file (*.vhd)
dct.vhd
The verilog synthesized using Synplicity (Synplify Pro) a
www.eeworm.com/read/492004/6429646
txt readme.txt
XAPP610 Zip file contains
The word document for DCT
Verilog files (*.v)
dct.v
test_dct.v
Vhdl file (*.vhd)
dct.vhd
The verilog synthesized using Synplicity (Synplify Pro) a
www.eeworm.com/read/484356/6586175
m transformpathfromnu.m
function [alphamat,alpha0vec,lambdavec,nuvec]=TransformPathFromNu(alphamat,alpha0vec,lambdavec,nuvec,Nbapp);
N=length(nuvec);
%Nbapp=size(xapp,1);
%nuvec=fliplr(linspace(min(lambdavec)/Nbapp,max(
www.eeworm.com/read/262186/11602656
m transformpathfromnu.m
function [alphamat,alpha0vec,lambdavec,nuvec]=TransformPathFromNu(alphamat,alpha0vec,lambdavec,nuvec,Nbapp);
N=length(nuvec);
%Nbapp=size(xapp,1);
%nuvec=fliplr(linspace(min(lambdavec)/Nbapp,max(
www.eeworm.com/read/233700/14142903
txt readme.txt
XAPP610 Zip file contains
The word document for DCT
Verilog files (*.v)
dct.v
test_dct.v
Vhdl file (*.vhd)
dct.vhd
The verilog synthesized using Synplicity (Synplify Pro) a
www.eeworm.com/read/211682/15175583
txt readme.txt
XAPP577 version 1.2 reference design files:
Verilog Directory:
hd_sep_demo.v: Top-level module for the separate Rx & Tx demo
hd_sep_demo.ucf: Contraints file for the sep
www.eeworm.com/read/13911/287227
m exsimulframetest.m
clear all
close all
%
% parameters of the model
%
nbtrain=100;
MaxIterBF=500;
lambda=[1 1 5];
level=[0 1;2 3;4 5];
noise=0.1;
nf=100;
name='Doppler';
[xapp,yapp,xtest,ytest