readme.txt

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

XAPP577 version 1.2 reference design files:

Verilog Directory:
    hd_sep_demo.v:           Top-level module for the separate Rx & Tx demo
    hd_sep_demo.ucf:         Contraints file for the separate Rx & Tx demo

    hd_pass_demo.v:          Top-level module for the pass-through demo
    hd_pass_demo.ucf:        Constraints file for the pass-through demo
    
    hd_pass_ics664.v:        Top-level module for the pass-through demo using ICS664
    hd_pass_ics664.ucf:      Constraints file for the pass-through demo using ICS664           
    
    hdsdi_autodetect_ln.v:   HD-SDI video format detector
    hdsdi_crc.v:             HD-SDI CRC generator
    hdsdi_decoder.v:         HD-SDI decoder
    hdsdi_encoder.v:         HD-SDI encoder
    hdsdi_framer_mult.v:     HD-SDI framer
    hdsdi_insert_crc.v:      Inserts formatted CRC values after EAV on each line
    hdsdi_insert_ln.v:       Inserts formatted line numbers after EAV on each line
    hdsdi_rio.v:             Wrapper around RocketIO transceiver with BREFCLKs selected
    hdsdi_rio_refclk.v:      Wrapper around RocketIO transceiver with REFCLKs selected 
    hdsdi_rx.v:              HD-SDI receiver data path
    hdsdi_rx2.v:             Slightly modified version of hdsdi_rx.v.
    hdsdi_rx_autorate.v:     HD-SDI bit rate detection
    hdsdi_rx_crc.v:          HD-SDI CRC error checker
    hdsdi_rx_timing.v:       Generates various video timing signals from received video
    hdsdi_tx_path.v:         HD-SDI transmitter data path
    led_blink_counter.v:     Clock divider used to generate low frequency signals
                             blink the LEDs
    led_control.v:           LED control module
    multigenHD_horz_logo.v:  Horizontal module for video pattern generator with
                             Xilinx logo generation included
    multigenHD_logo.v:       Top level of the video pattern generator with support
                             for Xilinx logo generation
    multigenHD_output.v:     Output portion of the video pattern generator
    multigenHD_vert.v:       Vertical module of the video pattern generator
    pd_HD_VCXO.v:            Phase detector for HD video rates -- used to lock
                             a VCXO to the recovered video clock
    phasedetHD.v:            Wrapper around the pd_HD_VCXO.v file
    rx_heartbeat.v:          Generates a heartbeat indicator by dividing the
                             occurrances of the TRS symbols down to a visible
                             frequency
    smpte_encoder.v:         10-bit SDI encoder module used in the hdsdi_encoder
                             module


VHDL Directory:
    This directory contains VHDL versions of the sames files listed above.
    It also contains the VHDL package files hdsdi_pkg.vhd and multigenHD_pkg.vhd.


Revision History
----------------
Release 1.2: 2006/01/10:

The framer files were updated to fix an issue where a very rare, but legal,
input pattern could cause the TRS detector to detect a TRS where one did not
exist. The framers are now slightly larger (about 7% more LUTs are required)
in order to detect the full 60-bit TRS sequence rather than the subset that
was previously detected. Both the hdsdi_framer_mult.v and hdsdi_framer_mult.vhd
files were modified with the same fix.

The multigenHD_logo.v file was modified to add a new parameter called VIRTEX4.
If this parameter is defined, the multigenHD_logo module will be synthesized
with DSP48 primitives instead of MULT18X18 primitives. The VHDL version of
multigenHD_logo does not have this same capability.

Release 1.1: 2005/06/24:

The hdsdi_autodetect_ln files, and the VHDL-only hdsdi_pkg.vhd file, were
updated to include support for detecting the 720p 50Hz video format. The
hdsdi_autodetect_ln file can now detect both 720p50 and 720p60.

The UCF files were modified slightly to use / as the hierarchy separator to
match the XST default starting in ISE 7.1.

Release 1.0: 2004/12/09:

Initial release.