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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_less_than is
generic(
width_a : integer := 6;
width_b : integer := 6;
sgate_representation: integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stx_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_fifo is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_decoder is
generic(
width_i : integer := 6;
width_o : integer := 6
);
port(
i :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altfp_mult is
generic(
width_exp : integer := 8;
width_man : integer := 23;
dedicated_multiplier_circuitry: st
readme.txt
一、 设计目的
1、学习<mark>Verilog</mark> HDL的设计技巧
2、学习串行EEPROM AT24C256的工作原理
3、掌握8051编程技术并了解I2C总线数据传输协议
4、学习嵌入式逻辑分析仪的使用
二、设计内容
利用拨码开关为可编程器件输入读写命令和相应的地址、数据，8051 P1读入可编程器件设定的命令字并根据可编程器件的设置进行读写操作（P2），读出来的数据通过P0输出给 ...
cmos_fifo_usb_syn.prj
#add_file options
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/two_port1280x8/two_port1280x8.v"
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/usb_fifo32x16/usb_fifo32x16.v"
add_f
run_options.txt
#-- Synplicity, Inc.
#-- Version Synplify 8.8A1
#-- Project file H:\fpga_test\cmos_fifo_usb\synthesis\run_options.txt
#-- Written on Wed May 21 14:37:58 2008
#add_file options
add_file -veril