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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ad9777_spi_interface is
port(
spi_ncs : in vl_logic;
spi_sck : in vl_logic;
spi_sdio : in
main.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
sum_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
main.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
encode_4_lsb.v
//
// Module: ENCODE_4_LSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-proceso
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Alu_RISC is
generic(
word_size : integer := 16;
op_size : integer := 12;
NOP : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity control is
generic(
state_reset : integer := 9;
state_spare : integer := 8
);
port(
clk1 : in
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE