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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_register is
generic(
width : integer := 8
);
port(
data_in : in vl_logic_vector;
data_ou
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
i2c_altera.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
spusnoop.v
// Produced by /usr/class/ee272/bin/snoopgen from file s.in
// Remember to run Verilog with -x if any variables are subscripted
// 2 Clock phases: phi1 phi2
// Input, Verilog: decisions_b_s1, irsi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity time_screen_set is
generic(
Time_screen : integer := 1;
Time_set : integer := 2;
Date_set : integer := 4