i2c_altera.qsf

filter,很不错,大家可以看以下

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		I2C_ALTERA_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_parameter -name SMART_RECOMPILE ON
set_parameter -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:09:10  AUGUST 10, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP2"
set_global_assignment -name VERILOG_FILE source720_576_25Hz.v
set_global_assignment -name VERILOG_FILE sync_gen.v
set_global_assignment -name VERILOG_FILE vga_out.v
set_global_assignment -name VERILOG_FILE Command.v
set_global_assignment -name VERILOG_FILE control_interface.v
set_global_assignment -name VERILOG_FILE datacnl.v
set_global_assignment -name VERILOG_FILE mesure_card_top.v
set_global_assignment -name VERILOG_FILE Params.v
set_global_assignment -name VERILOG_FILE ram2k_8to512_32.v
set_global_assignment -name VERILOG_FILE ram512_32.v
set_global_assignment -name VERILOG_FILE receive_pal.v
set_global_assignment -name VERILOG_FILE rom0p392_Cb.v
set_global_assignment -name VERILOG_FILE rom0p813_Cr.v
set_global_assignment -name VERILOG_FILE rom1p164_Y.v
set_global_assignment -name VERILOG_FILE rom1p596_Cr.v
set_global_assignment -name VERILOG_FILE rom2p017_Cb.v
set_global_assignment -name VERILOG_FILE sdr_data_path.v
set_global_assignment -name VERILOG_FILE sdr_sdram.v
set_global_assignment -name VERILOG_FILE sender_vga.v
set_global_assignment -name VERILOG_FILE add_mask.v
set_global_assignment -name VERILOG_FILE reset_gen.v
set_global_assignment -name VERILOG_FILE mask_rom.v
set_global_assignment -name VERILOG_FILE receiver_2.v
set_global_assignment -name VERILOG_FILE receiver.v
set_global_assignment -name VERILOG_FILE Led_run.v
set_global_assignment -name VERILOG_FILE vga_vl.v
set_global_assignment -name VERILOG_FILE filter.v
set_global_assignment -name VERILOG_FILE i2c_cmd.v
set_global_assignment -name AHDL_FILE I2C.TDF
set_global_assignment -name BDF_FILE I2C_ALTERA.bdf
set_global_assignment -name VERILOG_FILE clk_div.v
set_global_assignment -name VERILOG_FILE i2c_cmd_7128.v
set_global_assignment -name VERILOG_FILE clk_gen.v
set_global_assignment -name SIGNALTAP_FILE VGATEST.stp
set_global_assignment -name SIGNALTAP_FILE VIDEO_7113.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE test_qd_head.stp
set_global_assignment -name SIGNALTAP_FILE test_frame_sync.stp

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_153 -to SYSCLK
set_location_assignment PIN_240 -to RST
set_location_assignment PIN_21 -to SCL
set_location_assignment PIN_20 -to SDA
set_location_assignment PIN_29 -to PCLK
set_location_assignment PIN_48 -to PDATA[0]
set_location_assignment PIN_47 -to PDATA[1]
set_location_assignment PIN_46 -to PDATA[2]
set_location_assignment PIN_45 -to PDATA[3]
set_location_assignment PIN_44 -to PDATA[4]
set_location_assignment PIN_43 -to PDATA[5]
set_location_assignment PIN_42 -to PDATA[6]
set_location_assignment PIN_41 -to PDATA[7]
set_location_assignment PIN_23 -to P_HS
set_location_assignment PIN_39 -to P_VS
set_location_assignment PIN_162 -to ENC_CLK
set_location_assignment PIN_141 -to ENC_DATA[0]
set_location_assignment PIN_140 -to ENC_DATA[1]
set_location_assignment PIN_139 -to ENC_DATA[2]
set_location_assignment PIN_138 -to ENC_DATA[3]
set_location_assignment PIN_137 -to ENC_DATA[4]
set_location_assignment PIN_136 -to ENC_DATA[5]
set_location_assignment PIN_135 -to ENC_DATA[6]
set_location_assignment PIN_134 -to ENC_DATA[7]
set_location_assignment PIN_159 -to ENC_HS
set_location_assignment PIN_160 -to ENC_VS
set_location_assignment PIN_156 -to SCL_ENC
set_location_assignment PIN_158 -to SDA_ENC
set_location_assignment PIN_181 -to flash_ce
set_location_assignment PIN_3 -to flash_oe
set_location_assignment PIN_4 -to flash_rw
set_location_assignment PIN_176 -to LED[0]
set_location_assignment PIN_177 -to LED[1]
set_location_assignment PIN_178 -to LED[2]
set_location_assignment PIN_179 -to LED[3]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY I2C_ALTERA
set_global_assignment -name USER_LIBRARIES "f:\\i2c_altera"
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"

# Assembler Assignments
# =====================
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name GLITCH_INTERVAL "1 ns"
set_global_assignment -name VECTOR_INPUT_SOURCE I2C_ALTERA.vwf

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP off
set_global_assignment -name USE_SIGNALTAP_FILE VIDEO_7113.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------