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library verilog; use verilog.vl_types.all; entity cpu_admux is port( addr : out vl_logic_vector(12 downto 0); pc_addr : in vl_logic_vector(12 downto 0);

library verilog; use verilog.vl_types.all; entity dac_test_black_box1_wrapper is port( din : in vl_logic_vector(11 downto 0); rstn : in vl_logic;

library verilog; use verilog.vl_types.all; entity stratix_mac_mult_internal is generic( dataa_width : integer := 18; datab_width : integer := 18; dataout_width :

library verilog; use verilog.vl_types.all; entity leg_mult is port( clk : in vl_logic; dataa : in vl_logic_vector(31 downto 0); datab

library verilog; use verilog.vl_types.all; entity leg_shifter is port( din : in vl_logic_vector(31 downto 0); dout : out vl_logic_vector(31 downto 0);

library verilog; use verilog.vl_types.all; entity ddr_command is port( clk : in vl_logic; reset_n : in vl_logic; saddr : in vl_log

library verilog; use verilog.vl_types.all; entity mt46v4m16 is generic( addr_bits : integer := 12; data_bits : integer := 16; col_bits : integer := 8;

library verilog; use verilog.vl_types.all; entity test is end test;

library verilog; use verilog.vl_types.all; entity glbl is end glbl;

library verilog; use verilog.vl_types.all; entity testbench is end testbench;