_primary.vhd

来自「使用ＭＡＴＬＡＢ工具」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity dac_test_black_box1_wrapper is
    port(
        din             : in     vl_logic_vector(11 downto 0);
        rstn            : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        dout            : out    vl_logic_vector(31 downto 0)
    );
end dac_test_black_box1_wrapper;