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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_iv_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_hstl_iv_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_sstl3_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_clk_div is
generic(
divide_by : integer := 2;
divider_delay : integer := 0
);
port(
clkdv : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s2 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_lut2 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
adr0 : in