_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity x_clk_div is
    generic(
        divide_by       : integer := 2;
        divider_delay   : integer := 0
    );
    port(
        clkdv           : out    vl_logic;
        cdrst           : in     vl_logic;
        clkin           : in     vl_logic
    );
end x_clk_div;