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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dchufa is
port(
clk : in vl_logic;
data_in : in vl_logic_vector(7 downto 0);
data_out :
test.tbw
version 3
D:/xilinx/lianxi/diexingbianhuan/lian.vf
lian
VERILOG
VERILOG
test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
150
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_hstl_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_sstl3_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand2b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl3_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl3_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i