test.tbw

在ise下设计的蝶形变换程序

version 3
D:/xilinx/lianxi/diexingbianhuan/lian.vf
lian
VERILOG
VERILOG
test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
Aim_in
clk
Are_in
clk
Bim_in
clk
Bre_in
clk
Dim_out
clk
Dre_out
clk
Eim_out
clk
Ere_out
clk
c_in
clk
cms_in
clk
cps_in
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Dim_out_DIFF
Dre_out_DIFF
Eim_out_DIFF
Ere_out_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
Aim_in
Are_in
Bim_in
Bre_in
c_in
cms_in
cps_in
Dim_out
Dre_out
Eim_out
Ere_out
SIGNAL_ORDER_END
-X-X-X-