代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_rx_a1a2_patdet is
port(
clk : in vl_logic;
softreset : in vl_logic;
sync_comp_eq
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_mac_mult_internal is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dpram_segment is
generic(
\Tout\ : integer := 0;
\Taa\ : integer := 0;
\Tdd\ : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom_segment is
generic(
\Tout\ : integer := 0;
\Taa\ : integer := 0;
\Trc\ : integer := 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram_segment is
generic(
rd_d_wr : integer := 0;
\Tout\ : integer := 0;
\Twr\ : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_dp is
generic(
lpm_width : integer := 1;
lpm_widthad : integer := 1;
lpm_indata : string := "REGIS
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_compare is
generic(
lpm_width : integer := 1;
lpm_representation: string := "UNSIGNED";
lpm_pipeline : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_divide is
generic(
lpm_widthn : integer := 1;
lpm_widthd : integer := 1;
lpm_nrepresentation: string := "UN
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_bustri is
generic(
lpm_width : integer := 1;
lpm_type : string := "lpm_bustri";
lpm_hint : string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_dq is
generic(
lpm_width : integer := 1;
lpm_widthad : integer := 1;
lpm_indata : string := "REGIS