_primary.vhd

一个非常好的dc使用书籍 一个非常好的dc使用书籍

library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_rx_a1a2_patdet is
    port(
        clk             : in     vl_logic;
        softreset       : in     vl_logic;
        sync_comp_eq    : in     vl_logic_vector(15 downto 0);
        a1a2size        : in     vl_logic;
        a1a2_hit        : out    vl_logic_vector(7 downto 0);
        a1a1a2a2_hit    : out    vl_logic_vector(7 downto 0)
    );
end altgxb_hssi_rx_a1a2_patdet;