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library verilog; use verilog.vl_types.all; entity ALU_ARM7 is port( Alu_A : in vl_logic_vector(31 downto 0); Alu_B : in vl_logic_vector(31 downto 0);

library verilog; use verilog.vl_types.all; entity registerfile is port( RF_Addr_A : in vl_logic_vector(3 downto 0); RF_Addr_B : in vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity Processing_Unit is generic( word_size : integer := 16; op_size : integer := 12; Sel1_size : integer :=

Analysis & Synthesis report for HMB_MAX Sat Jun 30 13:49:05 2007 Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------

Version 7.0 Build 33 02/05/2007 SJ Web Edition 30 1704 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- --

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

library verilog; use verilog.vl_types.all; entity EMIF_COM is port( ARE : in vl_logic; AOE : in vl_logic; AWE : in vl_logic;

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

library verilog; use verilog.vl_types.all; entity b_task is port( clk_2_5m : in vl_logic; rst : in vl_logic; nd_b : in vl_logic;

library verilog; use verilog.vl_types.all; entity stratix_mac_mult_internal is generic( dataa_width : integer := 18; datab_width : integer := 18; dataout_width :