mux.map.qmsg

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 09 15:05:29 2008 " "Info: Processing started: Tue Dec 09 15:05:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mux -c mux " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux -c mux" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "mux E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v " "Warning: Entity \"mux\" obtained from \"E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux " "Info: Found entity 1: mux" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mux " "Info: Elaborating entity \"mux\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "d\[0\] VCC " "Warning: Pin \"d\[0\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] VCC " "Warning: Pin \"en\[1\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] VCC " "Warning: Pin \"en\[2\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] VCC " "Warning: Pin \"en\[3\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] VCC " "Warning: Pin \"en\[4\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] VCC " "Warning: Pin \"en\[5\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] VCC " "Warning: Pin \"en\[6\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning: Pin \"en\[7\]\" stuck at VCC" {  } { { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 15:05:33 2008 " "Info: Processing ended: Tue Dec 09 15:05:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}