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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_compare is
generic(
lpm_width : integer := 1;
lpm_representation: string := "UNSIGNED";
lpm_pipeline : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_divide is
generic(
lpm_widthn : integer := 1;
lpm_widthd : integer := 1;
lpm_nrepresentation: string := "UN
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_bustri is
generic(
lpm_width : integer := 1;
lpm_type : string := "lpm_bustri";
lpm_hint : string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_dq is
generic(
lpm_width : integer := 1;
lpm_widthad : integer := 1;
lpm_indata : string := "REGIS
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_io is
generic(
lpm_type : string := "lpm_ram_io";
lpm_width : integer := 1;
lpm_widthad : intege
i2c_altera.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cic_filter is
port(
clk : in vl_logic;
rst : in vl_logic;
cic_in : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cic_inter is
port(
clk : in vl_logic;
clk_inter : in vl_logic;
rst : in vl_logic
sram_test.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {sram_test.vo sram_test_v.sdo}}
}
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_min is
generic(
K : integer := 8
);
port(
reset : in vl_logic;
data_clk : i