i2c_altera.map.qmsg

详细介绍SDRAM原理的中文电子书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 27 22:15:54 2006 " "Info: Processing started: Mon Mar 27 22:15:54 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off I2C_ALTERA -c I2C_ALTERA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off I2C_ALTERA -c I2C_ALTERA" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Y2Cb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Y2Cb.v" { { "Info" "ISGN_ENTITY_NAME" "1 Y2Cb " "Info: Found entity 1: Y2Cb" {  } { { "Y2Cb.v" "" { Text "D:/RedLogic/VBuffer/Y2Cb.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_color_gen_rgb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom_color_gen_rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_color_gen_RGB " "Info: Found entity 1: rom_color_gen_RGB" {  } { { "rom_color_gen_rgb.v" "" { Text "D:/RedLogic/VBuffer/rom_color_gen_rgb.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram256_32to1k_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram256_32to1k_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram256_32to1k_8 " "Info: Found entity 1: ram256_32to1k_8" {  } { { "ram256_32to1k_8.v" "" { Text "D:/RedLogic/VBuffer/ram256_32to1k_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2k_2to512_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram2k_2to512_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram2k_2to512_8 " "Info: Found entity 1: ram2k_2to512_8" {  } { { "ram2k_2to512_8.v" "" { Text "D:/RedLogic/VBuffer/ram2k_2to512_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "arbiter.v(131) " "Warning: (10273) Verilog HDL warning at arbiter.v(131): extended using \"x\" or \"z\"" {  } { { "arbiter.v" "" { Text "D:/RedLogic/VBuffer/arbiter.v" 131 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arbiter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arbiter.v" { { "Info" "ISGN_ENTITY_NAME" "1 arbiter " "Info: Found entity 1: arbiter" {  } { { "arbiter.v" "" { Text "D:/RedLogic/VBuffer/arbiter.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_sel.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_sel " "Info: Found entity 1: rom_sel" {  } { { "rom_sel.v" "" { Text "D:/RedLogic/VBuffer/rom_sel.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_cmd_two.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_cmd_two.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_cmd_two " "Info: Found entity 1: i2c_cmd_two" {  } { { "i2c_cmd_two.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd_two.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_vl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_vl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_vl " "Info: Found entity 1: vga_vl" {  } { { "vga_vl.v" "" { Text "D:/RedLogic/VBuffer/vga_vl.v" 58 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_32 " "Info: Found entity 1: ram512_32" {  } { { "ram512_32.v" "" { Text "D:/RedLogic/VBuffer/ram512_32.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom2p017_cb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom2p017_cb.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom2p017_Cb " "Info: Found entity 1: rom2p017_Cb" {  } { { "rom2p017_cb.v" "" { Text "D:/RedLogic/VBuffer/rom2p017_cb.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0p813_cr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom0p813_cr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0p813_Cr " "Info: Found entity 1: rom0p813_Cr" {  } { { "rom0p813_cr.v" "" { Text "D:/RedLogic/VBuffer/rom0p813_cr.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1p164_y.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom1p164_y.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom1p164_Y " "Info: Found entity 1: rom1p164_Y" {  } { { "rom1p164_y.v" "" { Text "D:/RedLogic/VBuffer/rom1p164_y.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1p596_cr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom1p596_cr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom1p596_Cr " "Info: Found entity 1: rom1p596_Cr" {  } { { "rom1p596_cr.v" "" { Text "D:/RedLogic/VBuffer/rom1p596_cr.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0p392_cb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom0p392_cb.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0p392_Cb " "Info: Found entity 1: rom0p392_Cb" {  } { { "rom0p392_cb.v" "" { Text "D:/RedLogic/VBuffer/rom0p392_cb.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_out.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_out.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_out " "Info: Found entity 1: vga_out" {  } { { "vga_out.v" "" { Text "D:/RedLogic/VBuffer/vga_out.v" 40 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "image_ntsc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file image_ntsc.v" { { "Info" "ISGN_ENTITY_NAME" "1 image_NTSC " "Info: Found entity 1: image_NTSC" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 40 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "params_dsp.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file params_dsp.v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "blank_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file blank_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 blank_gen " "Info: Found entity 1: blank_gen" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params.v(35) " "Warning: (10274) Verilog HDL macro warning at params.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params.v" "" { Text "D:/RedLogic/VBuffer/params.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "command.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Info: Found entity 1: command" {  } { { "command.v" "" { Text "D:/RedLogic/VBuffer/command.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params_dsp.v(35) " "Warning: (10274) Verilog HDL macro warning at params_dsp.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params_dsp.v" "" { Text "D:/RedLogic/VBuffer/params_dsp.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "command_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file command_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 command_dsp " "Info: Found entity 1: command_dsp" {  } { { "command_dsp.v" "" { Text "D:/RedLogic/VBuffer/command_dsp.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE Params.v(35) " "Warning: (10274) Verilog HDL macro warning at Params.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "Params.v" "" { Text "D:/RedLogic/VBuffer/Params.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Info: Found entity 1: control_interface" {  } { { "control_interface.v" "" { Text "D:/RedLogic/VBuffer/control_interface.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE Params_dsp.v(35) " "Warning: (10274) Verilog HDL macro warning at Params_dsp.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "Params_dsp.v" "" { Text "D:/RedLogic/VBuffer/Params_dsp.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_interface_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_interface_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface_dsp " "Info: Found entity 1: control_interface_dsp" {  } { { "control_interface_dsp.v" "" { Text "D:/RedLogic/VBuffer/control_interface_dsp.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datacnl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datacnl.v" { { "Info" "ISGN_ENTITY_NAME" "1 datacnl " "Info: Found entity 1: datacnl" {  } { { "datacnl.v" "" { Text "D:/RedLogic/VBuffer/datacnl.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datacnl_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datacnl_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 datacnl_dsp " "Info: Found entity 1: datacnl_dsp" {  } { { "datacnl_dsp.v" "" { Text "D:/RedLogic/VBuffer/datacnl_dsp.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "image0109.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file image0109.v" { { "Info" "ISGN_ENTITY_NAME" "1 image0109 " "Info: Found entity 1: image0109" {  } { { "image0109.v" "" { Text "D:/RedLogic/VBuffer/image0109.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "clk mesure_card_top.v(132) " "Warning: Verilog HDL net warning at mesure_card_top.v(132): created undeclared net \"clk\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "r_req_raw mesure_card_top.v(194) " "Warning: Verilog HDL net warning at mesure_card_top.v(194): created undeclared net \"r_req_raw\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 194 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "r_ack_raw mesure_card_top.v(195) " "Warning: Verilog HDL net warning at mesure_card_top.v(195): created undeclared net \"r_ack_raw\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 195 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "s_ram_wen mesure_card_top.v(259) " "Warning: Verilog HDL net warning at mesure_card_top.v(259): created undeclared net \"s_ram_wen\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 259 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "s_ack_mask mesure_card_top.v(366) " "Warning: Verilog HDL net warning at mesure_card_top.v(366): created undeclared net \"s_ack_mask\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 366 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "r_ack_mask mesure_card_top.v(460) " "Warning: Verilog HDL net warning at mesure_card_top.v(460): created undeclared net \"r_ack_mask\"" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 460 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mesure_card_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mesure_card_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesure_card_top " "Info: Found entity 1: mesure_card_top" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params.v(35) " "Warning: (10274) Verilog HDL macro warning at params.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params.v" "" { Text "D:/RedLogic/VBuffer/params.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "params.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file params.v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram1k_8to256_32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram1k_8to256_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram1k_8to256_32 " "Info: Found entity 1: ram1k_8to256_32" {  } { { "ram1k_8to256_32.v" "" { Text "D:/RedLogic/VBuffer/ram1k_8to256_32.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram1k_8to512_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram1k_8to512_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram1k_8to512_16 " "Info: Found entity 1: ram1k_8to512_16" {  } { { "ram1k_8to512_16.v" "" { Text "D:/RedLogic/VBuffer/ram1k_8to512_16.v" 42 -1 0 } }  } 0}  } {  } 0}