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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clkdll is
generic(
clkdv_divide : real := 2.000000;
duty_cycle_correction: string := "TRUE";
factory_jf : inte
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or2b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_mult18x18 is
generic(
cds_action : string := "ignore"
);
port(
p : out vl_logic_vector(35 downto
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_startup is
port(
bus_reset : out vl_logic;
ghigh_b : out vl_logic;
gsr : out vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_flip_flop_sclr_v2_0 is
generic(
zero_string : integer := 0
);
port(
d : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand_a_notb_fd_v4 is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_conj_reg_v2_0 is
generic(
b : integer := 16
);
port(
clk : in vl_logic;
ce
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_b_c_notd_v2 is
port(
a_in : in vl_logic;
b_in : in vl_logic;
c_in : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand_a_notb_fd_v2 is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_mem_ctrl_v2_0 is
generic(
points_power : integer := 5;
w_width : integer := 16;
b : intege