_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_mem_ctrl_v2_0 is
    generic(
        points_power    : integer := 5;
        w_width         : integer := 16;
        b               : integer := 16;
        memory_configuration: integer := 3;
        data_memory     : string  := "distributed_memory";
        ainit_val       : string  := "1";
        start_to_bfly_input_latency: integer := 3;
        bfly_res_avail_latency: integer := 16;
        init_value      : string  := "000000";
        count_by_value  : string  := "000001";
        string_31       : string  := "11111";
        ainit_val_bank  : string  := "0";
        ninety_six      : string  := "1100000";
        one_string_1    : string  := "00001";
        ainit_val_1     : string  := "00000";
        sinit_val_1     : string  := "00000";
        thirty_one_1    : string  := "11111";
        string_29       : string  := "11101";
        string_28       : string  := "11100"
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        start           : in     vl_logic;
        reset           : in     vl_logic;
        mwr             : in     vl_logic;
        mrd             : in     vl_logic;
        usr_loading_addr: in     vl_logic;
        address         : in     vl_logic_vector;
        usr_load_addr   : in     vl_logic_vector;
        initial_data_load_x: in     vl_logic;
        rank_number     : in     vl_logic_vector(1 downto 0);
        bfly_res_avail  : in     vl_logic;
        e_bfly_res_avail: in     vl_logic;
        e_done_int      : in     vl_logic;
        done_int        : in     vl_logic;
        result_avail    : in     vl_logic;
        xbar_y          : out    vl_logic;
        ext_to_xbar_y_temp_out: out    vl_logic_vector(0 downto 0);
        io              : out    vl_logic;
        eio             : out    vl_logic;
        io_pulse        : out    vl_logic;
        eio_pulse_out   : out    vl_logic;
        reset_io_out    : out    vl_logic;
        we_dmem         : out    vl_logic;
        we_dmem_dms     : out    vl_logic;
        wex_dmem_tms    : out    vl_logic;
        wey_dmem_tms    : out    vl_logic;
        d_a_dmem_dms_sel: out    vl_logic;
        wea_x           : out    vl_logic;
        wea_y           : out    vl_logic;
        web_x           : out    vl_logic;
        web_y           : out    vl_logic;
        ena_x           : out    vl_logic;
        ena_y           : out    vl_logic;
        data_sel        : out    vl_logic_vector(1 downto 0);
        address_select  : out    vl_logic_vector(1 downto 0);
        address_select_dms_out: out    vl_logic_vector(0 downto 0);
        reading_result  : out    vl_logic;
        writing_result  : out    vl_logic;
        wr_addr         : out    vl_logic_vector;
        addra_dmem      : out    vl_logic_vector;
        addra_x_dmem    : out    vl_logic_vector;
        addra_y_dmem    : out    vl_logic_vector;
        addrb_dmem      : out    vl_logic_vector;
        addrb_dmem_dms  : out    vl_logic_vector;
        addrb_dmem_tms  : out    vl_logic_vector;
        rd_addrb_x      : out    vl_logic_vector;
        rd_addrb_y      : out    vl_logic_vector
    );
end vfft32_mem_ctrl_v2_0;