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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vs_hs is
port(
clk : in vl_logic;
rst : in vl_logic;
hs : out vl_logic;
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
ps2_keyboard_interface.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity main is
port(
clk : in vl_logic;
reset : in vl_logic;
io_out : out vl_logic_vect
_info
m255
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cModel Technology
dJ:\Project_Navigator_Demo\alu_vlog
valu
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VTg9OV4IAD:W_bGR;6C@j31
dJ:\temp\exam\HDLBencher-ALU\alu_vlog
w1036717816
FALU.V
L0 5
OE;L;5.5f;17
r1
31
o-93