_primary.vhd

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity vs_hs is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        hs              : out    vl_logic;
        vs              : out    vl_logic;
        counths         : out    vl_logic_vector(9 downto 0);
        countvs         : out    vl_logic_vector(9 downto 0)
    );
end vs_hs;