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Verilog 的代码
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
_info
m255
cModel Technology
dE:\刘韬\MY_WORK\FPGA\程序\I2C
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
w1059855545
FC:/Program Files/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7e;17
r1
31
vi2c_slave_model
_info
m255
cModel Technology
dE:\刘韬\MY_WORK\FPGA\程序\I2C
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
w1059855545
FC:/Program Files/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7e;17
r1
31
vi2c_slave_model
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity reg8r is
port(
clk : in vl_logic;
\in\ : in vl_logic_vector(7 downto 0);
\out\ :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity IndiAddr is
port(
clk : in vl_logic;
rst : in vl_logic;
addr : in vl_logic_
compare_test.v
//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test1
//filename : file_testbnech
//author : wangyang
//data : 2007/8/2
//version : 1.0
//
//