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byte_crc.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
11
1012
OFF
OFF
OFF
OFF
ON
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ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tb_ADPLL is
generic(
del : integer := 1;
cnt_size : integer := 4;
cycle_time : integer := 200
build_xl.mak
#
# sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = read_vector_tf.c \
veriuser_XL.c
OBJS = $
build_xl.mak
#
# sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = hello_acc.c \
show_value_acc.c \
build_xl.mak
#
# sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = \
my_monitor_acc.c \
veriuser_XL.
veriuser_vcs.tab
// Example Synopsys VCS PLI table to register PLI applications
// For the book, "The Verilog PLI Handbook"
$my_monitor data=0 check=PLIbook_MyMonitor_checktf call=PLIbook_MyMonitor_calltf acc+
list_path_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
list_path_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 9, 1999 14:19:58
Verilog_XL_Turbo_NT 2.6.9 J
fetch_values_test.v
/**********************************************************************
* $test_acc_fetch_value example -- Verilog test bench source code
*
* Verilog test bench to test the $test_acc_fetch_value
sci_alu_combinational_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_combinational_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 12, 1999 10:33:25
Verilog_XL_Turbo_NT 2.6.
sci_alu_sequential_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_sequential_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 11, 1999 22:59:16
Verilog_XL_Turbo_NT 2.6.9