代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pulse_reg_v2 is
generic(
no : integer := 0;
yes : integer := 1
);
port(
sclr_in :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity subrevht is
generic(
input_width : integer := 8;
signed : integer := 1
);
port(
a : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v1_base is
generic(
c_has_ce : integer := 0;
c_has_code_err : integer := 1;
c_has_disp_err : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_b_c_notd is
port(
a_in : in vl_logic;
b_in : in vl_logic;
c_in : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v2_0_base is
generic(
c_force_code_disp: integer := 0;
c_force_code_val: string := "1010101010";
c_has_ce
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tsb32xvht is
generic(
output_width : integer := 8
);
port(
sdi : in vl_logic;
c :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v3_0_base is
generic(
c_has_ce : integer := 0;
c_has_code_err : integer := 1;
c_has_disp_err : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity almost_reg_v4 is
generic(
init_val : string := "0"
);
port(
a_in : in vl_logic;
b_in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tsb16svht is
generic(
output_width : integer := 8
);
port(
sdi : in vl_logic;
c :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v2_base is
generic(
c_has_ce : integer := 0;
c_has_code_err : integer := 1;
c_has_disp_err : integer