代码搜索结果
找到约 10,000 项符合
Verilog 的代码
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
half_clk.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Star
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity a_task is
port(
clk_2_5m : in vl_logic;
rst : in vl_logic;
nd_a : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SSC is
port(
req_c : in vl_logic;
did : in vl_logic_vector(2 downto 0);
req : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity router is
port(
reqin_east : in vl_logic;
din_east : in vl_logic_vector(33 downto 0);
ackout_east
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity datactl is
port(
data : out vl_logic_vector(7 downto 0);
\in\ : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity \register\ is
port(
opc_iraddr : out vl_logic_vector(15 downto 0);
data : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity adr is
port(
addr : out vl_logic_vector(12 downto 0);
fetch : in vl_logic;
ir_addr : i