_primary.vhd

关于乒乓操作的

library verilog;
use verilog.vl_types.all;
entity a_task is
    port(
        clk_2_5m        : in     vl_logic;
        rst             : in     vl_logic;
        nd_a            : in     vl_logic;
        indata_a        : in     vl_logic_vector(15 downto 0);
        out_a           : out    vl_logic_vector(15 downto 0);
        rdy_a           : out    vl_logic
    );
end a_task;