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all: sim SHELL = /bin/sh MS="-s" ########################################################################## # # DUT Sources # ########################################################################

library verilog; use verilog.vl_types.all; entity execute is port( clk : in vl_logic; reset : in vl_logic; exe_data1_ddd : in vl_logic_v

m255 o cModel Technology dC:\ipx_v1_000\mi2c\verilog\gate_sim vmi2c_tb I:ohH9zZZ^Aof]j1 ViTaGAh51MGAi^BUjCH;Vg3 w1000395789 Fe:/ipx/ipx_source/mi2c/verilog/sim/mi2c_tb.v L0 48 OE;L;5.5c;17 r1 3

library verilog; use verilog.vl_types.all; entity com_send is port( reset : in vl_logic; clk16x : in vl_logic; wren : in vl_logic;

# # Verilog Build requirements for RTL simulation of the Full Stripe Model # Device = epxa10 vlib work vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_stripe.

## # Verilog Build requirements for Timing simulation of the Full Stripe Model # Device = epxa10 vlib work vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_str

# # Verilog Build requirements for RTL simulation of the Full Stripe Model # Device = epxa10 vlib work vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_stripe.

## # Verilog Build requirements for Timing simulation of the Full Stripe Model # Device = epxa10 vlib work vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_str

#-- Synplicity, Inc. #-- Version 9.0 #-- Project file E:\programer_new\UART\project\synthesis\run_options.txt #-- Written on Tue Aug 19 09:08:56 2008 #add_file options add_file -verilog "E:/p

#add_file options add_file -verilog "E:/programer_new/UART/project/hdl/rec.v" add_file -verilog "E:/programer_new/UART/project/hdl/send.v" add_file -verilog "E:/programer_new/UART/project/hdl/uart_