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library verilog; use verilog.vl_types.all; entity reg5 is port( \in\ : in vl_logic_vector(4 downto 0); \out\ : out vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity reg3 is port( \in\ : in vl_logic_vector(2 downto 0); \out\ : out vl_logic_vector(2 downto 0);

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

Version 7.1 Build 156 04/30/2007 SJ Full Version 11 912 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths

library verilog; use verilog.vl_types.all; entity pllx2 is port( inclk0 : in vl_logic; areset : in vl_logic; c0 : out vl_logic;

library verilog; use verilog.vl_types.all; entity stratix_io is generic( operation_mode : string := "input"; ddio_mode : string := "none"; open_drain_output: strin

library verilog; use verilog.vl_types.all; entity altlvds_tx is generic( number_of_channels: integer := 1; deserialization_factor: integer := 4; registered_input: string :

library verilog; use verilog.vl_types.all; entity altaccumulate is generic( width_in : integer := 4; width_out : integer := 8; lpm_representation: string := "

library verilog; use verilog.vl_types.all; entity scfifo is generic( lpm_width : integer := 1; lpm_widthu : integer := 1; lpm_numwords : integer := 2;

library verilog; use verilog.vl_types.all; entity hcstratix_io is generic( operation_mode : string := "input"; ddio_mode : string := "none"; open_drain_output: str